Power optimization and/or bandwidth optimization of logic circuits up to now has been obtained by designing different logic parts with different bandwidth, to enable optimization of bandwidth and by this reduction of power consumption.
With regard to delay stages, the state of the art includes different possibilities.
The most usual way is to adjust a threshold level or a decision point along a flank and thereby shift a switch-over of a following stage forwards or backwards in time.
Another method is to add or subtract a capacitive load in a circuit stage for coarse adjustment and to change the current for fine adjustment.
A third method is to use diodes as collector loads. By varying the current through the diodes, the resistances of diodes will vary, which in turn changes the time constants of the circuit.